effect transistors are produced using ty's proprietary, NDC7001C general description features __ __________________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter n-channel p-channel units v dss drain-source voltage 50 -50 v v gss gate-source voltage - continuous 20 -20 v i d drain current - continuous (note 1a) 0.51 -0.34 a - pulsed 1.5 -1 p d maximum power dissipation (note 1a) 0.96 w (n ote 1b) 0.9 (no te 1c) 0.7 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 130 c/w r q jc thermal resistance, junction-to-case (note 1) 60 c/w these dual n and p-channel enhancement mode power field high cell density, dmos technology. this very high density process has been designed to minimize on-state resistance, provide rugged and reliable performance and fast switching. these devices is particularly suited for low voltage, low current, switching, and power supply applications . n-channel 0.51 a, 50v, r ds(on) = 2 w @ v gs =10v p-channel -0.34a, -50v. r ds(on ) = 5 w @ v gs =-10v. high density cell design for low r ds(on) . proprietary supersot tm -6 package design using copper lead frame for superior thermal and electrical capabilities. high saturation current . 1 5 4 6 3 2 supersot tm -6 1 of 3 4008-318-123 sales@twtysemi.com http://www.twtysemi.com product specification
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a n-ch 50 v v gs = 0 v, i d = -250 a p-ch -50 i dss zero gate voltage drain current v ds = 40 v , v gs = 0 v n-ch 1 a t j = 12 5c 500 v ds = -40 v, v gs = 0 v p-ch -1 t j = 12 5c -500 i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v all 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v all -100 na on characteristics (note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a n-ch 1 1.9 2.5 v t j = 12 5c 0.8 1.5 2.2 v ds = v gs , i d = -250 .a p-ch -1 -2.5 -3.5 t j = 12 5c -0.8 -2.2 -3 r ds(on) static drain-source on-resistance v gs = 10 v, i d = 0.51 a n-ch 1 2 w t j = 125c 1.7 3.5 v gs = 4.5 v, i d = 0.35 a 1.6 4 v gs = -10 v, i d = -0.34 a p-ch 2.5 5 t j = 125c 4 10 v gs = -4.5 v, i d = -0.25 a 5.3 7.5 i d (on) on-state drain current v gs = 10 v, v ds = 10 v n-ch 1.5 a v gs = -10 v, v ds = -10 v p-ch -1 g fs forward transconductance v ds = 10 v, i d = 0.51 a n-ch 400 ms v ds = -10 v, i d = -0.34 a p-ch 250 dynamic characteristics c iss input capacitance n-channel v ds = 25 v, v gs = 0 v, f = 1.0 mhz p-channel v ds = -25 v, v gs = 0 v, f = 1.0 mhz n-ch 20 pf p-ch 40 c oss output capacitance n-ch 13 pf p-ch 13 c rss reverse transfer capacitance n-ch 5 pf p-ch 4 2 of 3 4008-318-123 sales@twtysemi.com http://www.twtysemi.com NDC7001C product specification
electrical characteristics (t a = 25 o c unless otherwise noted) symbol parameters conditions type min typ max units switching ch aracteristics (note 2) t d(on) turn - on delay time n-channel v dd = 25 v, i d = 0.25 a , v gs = 10 v, r gen = 25 w p-channel v dd = -25 v, i d = -0.25 a , v gs = -10 v, r gen = 25 w n-ch 6 20 ns p-ch 14 20 t r turn - on rise time n-ch 6 20 p-ch 6 20 t d(off) turn - off delay time n-ch 11 20 p-ch 13 20 t f turn - off fall time n-ch 5 20 p-ch 6 20 q g total gate charge n-channel v ds = 25 v, i d = 0.51 a, v gs = 10 v p -channel v ds = -25 v, i d = -0.34 a, v gs = -10 v n-ch 1 nc p-ch 1.3 q gs gate-source charge n-ch 0.19 nc p-ch 0.23 q gd gate-drain charge n-ch 0.33 nc p-ch 0.38 drain-source diode characteristics i s maximum continuous source current n-ch 0.51 a p-ch -0.34 i sm maximum pulse source current (note 2) n-ch 1.5 a p-ch -1 v sd drain-source diode forward voltage v gs = 0 v, i s = 0.51 a (note 2) n-ch 0.8 1.2 v v gs = 0 v, i s = -0.34 a (note 2) p-ch -0.8 -1.2 notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja for single device operation using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 130 o c/w when mounted on a 0.125 in 2 pad of 2oz cpper. b. 140 o c/w when mounted on a 0.005 in 2 pad of 2oz cpper. c. 180 o c/w when mounted on a 0.0015 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 1a 1b 1c 3 of 3 4008-318-123 sales@twtysemi.com http://www.twtysemi.com NDC7001C product specification
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